The Design and Formal Verification of an Integrated Circuit for Use in a Floating-point Systolic Array Fast Fourier Transform Processor
Author | : Peter E. DelVecchio |
Publisher | : |
Total Pages | : 438 |
Release | : 1990 |
ISBN-10 | : CORNELL:31924052532045 |
ISBN-13 | : |
Rating | : 4/5 (45 Downloads) |
Download or read book The Design and Formal Verification of an Integrated Circuit for Use in a Floating-point Systolic Array Fast Fourier Transform Processor written by Peter E. DelVecchio and published by . This book was released on 1990 with total page 438 pages. Available in PDF, EPUB and Kindle. Book excerpt: